The present invention generally relates to voltage clamping circuits, and, more particularly, to voltage clamping circuits that include active low voltage devices.
Input/output (I/O) circuits are used to input and output electrical signals to and from integrated circuits (ICs) and are usually coupled to one or more I/O pins of an IC. I/O pins receive signals from external circuits and pass the received input signals to the corresponding I/O circuits. The I/O circuits pass the input signals to internal circuitry of the IC. The I/O circuits also transmit output signals received from the IC internal circuitry to the I/O pins, which in turn transmit these output signals to external circuits. Due to shrinking dimensions of ICs, among other reasons, IC supply voltages have been continuously declining, which necessitates use of low voltage (˜1.8V) devices, such as low-voltage transistors, in the I/O circuits.
However, such low voltage devices may be less reliable. For example, an I/O pin may be subjected to reflections, voltage over shoots, and voltage under shoots during data transmission, resulting in voltage spikes of about 1.0 volt above the I/O supply voltage and 1.0 volt below the I/O ground. Such voltage spikes can lead to failure of low voltage devices. When a circuit drives a data packet to an I/O circuit, the I/O circuit may exhibit poor performance if it is unpowered or under powered. Further, transistors in I/O circuits are susceptible to failure during pull-up transactions on the I/O pin. Specific compliance tests, such as Universal Serial Bus (USB) A/C stress test, may subject the transistors to voltages beyond their operating limits, causing them to fail. Thus, I/O circuits need to be protected from over shoot and under shoot voltages.
FIG. 1 shows a conventional I/O protection circuit 100 used for protecting an I/O circuit from over shoot and under shoot voltages. The I/O protection circuit 100 includes a plurality of constant-current diodes including first through fourth diodes 102a-102d (referred to collectively as 102), and an I/O pin 104. The four diodes 102 are connected in series, with a second terminal of the first diode 102a receiving a supply voltage VDDH, a first terminal of the fourth diode 102d connected to ground, and the I/O pin 104 coupled to a node between the second and third diodes 102b and 102c. The I/O pin 104 is connected to an I/O circuit (not shown) and transmits electrical signals received from an external circuit to the I/O circuit. The I/O circuit also is connected to an IC (not shown) and receives electrical signals transmitted from the IC to the I/O pin 104. When the I/O pin 104 is subjected to a voltage greater than twice the threshold voltage (Vt) of the diodes 102, a low-resistance path is enabled from the I/O pin 104 to the supply voltage terminal VDDH through the first and second diodes 102a and 102b. When the I/O pin 104 is subjected to a voltage that is less than twice Vt, a low-resistance path is enabled from ground through the third and fourth diodes 102c and 102d, to the I/O pin 104. The low-resistance path absorbs the over shoot or under shoot voltages and provides a clamped over shoot voltage having a magnitude of (VDDH+2Vt) and a clamped under shoot voltage having a magnitude of (−2Vt). However, the constant clamped magnitudes may exceed the reliability limits of the I/O circuit and the I/O protection circuit 100 may not protect the I/O circuit. Additionally, the magnitude of the output clamping voltage is dependent on the design technology of the I/O protection circuit 100.
Therefore, it would be advantageous to have a voltage clamping circuit that provides controlled lower clamped voltage and higher clamped current and that overcomes the above-mentioned limitations of existing voltage clamping circuits.